1. Field of the Invention
The present invention relates to a method of erasing a non-volatile semiconductor memory device having dispersed charge storing means (for example charge traps in a nitride film in a metal-oxide-nitride-oxide-semiconductor (MONOS) type and metal-nitride-oxide-semiconductor (MNOS) type, charge traps near the interface between a top insulating film and a nitride film, or fine particle conductors, etc.) inside a gate insulating film between a channel-forming region and a gate electrode of a memory transistor and performing, as its basic operation, injection of charges (electrons or holes) to the dispersed charge storing means for storage or withdrawing of the same and a such a non-volatile semiconductor memory device.
2. Description of the Related Art
Non-volatile semiconductor memories include, for example, the FG type wherein charge storing means (floating gate ) for holding charges is made planarly and, also, the MONOS type wherein charge storing means (charge traps) are made planarly disperse.
In an FG type non-volatile memory transistor, a floating gate comprised of polyorystalline silicon etc. is stacked on a channel-forming region of a semiconductor via a gate insulating film. A control gate is further stacked on the floating gate via an inter-gate insulating film comprised of an oxide-nitride-oxide (ONO) film etc.
On the other hand, in a MONOS type non-volatile memory transistor, a tunnel insulating film comprised for example of a silicon oxide film, an oxynitride film, etc., an interlayer Insulating film comprised of a nitride film, oxynitride film, etc., and a top insulating film comprised of a silicon oxide film are successively stacked on the channel-forming region of the semiconductor. A gate electrode is formed on the top insulating film.
In a MONOS type non-volatile semiconductor memory, carrier traps serving mainly for holding charges in the nitride film (SixNy (0 less than x less than 1, 0 less than y less than 1)) or at an interface between the top insulating film and the nitride film are discretely dispersed spatially (that is, in the planar direction and film thickness direction), so the charge holding characteristic depends on the energy and spatial distribution of the charge captured by the carrier trap in the SixNy film in addition to the tunnel insulating film thickness.
When a leakage current path locally occurs in the tunnel Insulating film, in the FG type, much of the charge passes through the leakage path and the charge holding characteristic is liable to decline, while in the MONOS type, since the charge storing means are spatially dispersed, the local charges around the leakage path pass through the leakage path and only locally leaks and therefore the charge holding characteristic of the overall memory device is resistant to decline.
Therefore, in the MONOS type, the problem of the decline of the charge holding characteristic caused by a tunnel insulating film becoming thinner is not as serious as in the FG type. Accordingly, the MONOS type is superior to the FG type in scaling of the tunnel oxide film in a fine memory transistor having an extremely short gate length.
In the above FG type non-volatile memory or MONOS type or other non-volatile memory where the charge storing means of the memory transistors are planarly dispersed, to reduce the cost per bit, increase the integration, and realize a large scale non-volatile memory, it is essential to realize a one-transistor type cell structure.
However, particularly in a MONOS type or other non-volatile memory, the mainstream is a two-transistor type wherein a selection transistor is connected to a memory transistor. Various studies are currently underway for establishing the one-transistor cell technique.
To establish the one-transistor cell technique, improvement of the disturb characteristic is necessary in addition to optimization of the element structure such as the gate insulating film including the charge storing means and improvement of the reliability. As one means for improving the disturb characteristic of a MONOS type non-volatile memory, studies are being conducted to set the tunnel insulating film thicker than the normal film thickness of 1.6 nm to 2.0 nm.
In a one-transistor cell, since there is no selection transistor in the cell, it is important to reduce the disturb characteristic of the memory transistor in non-selected cells connected to the same common line as a cell to be written in. The technique has already been proposed of applying an inhibit voltage to a source impurity region or drain impurity region of a non-selected memory transistor via a bit line or a source line at the time of writing or reading and thereby preventing erroneous writing and erroneous erasure of the non-selected memory transistor.
Summarizing the problems to be solved by the invention, in a MONOS or other non-volatile semiconductor memory with dispersed charge storing means, however, when the tunnel insulating film is made relatively thick in order to improve the disturb characteristic at the time of programming or a read operation, the erasure speed becomes relatively slow compared with the write speed. As a typical value, compared with a write speed of 0.1 to 1.0 msec, the erasure speed is 80 to 100 msec or two orders slower.
As another problem, in a non-volatile semiconductor memory, in block erasure, the cells in the write state and the cells in the erase state are simultaneously erased. If cells in the erase state are further erased at this time, there is the problem that the threshold voltage of part of the memory cells will become lower than the threshold voltage of the other memory cells due to excess erasing. This lowering of the threshold voltage causes an increase of the leakage current from the non-selected cells at the time of a read operation.
An object of the present invention is to provide a method of erasing a non-volatile semiconductor memory device capable of aligning both memory transistors in the erase state and memory transistors in the write state at a constant erased level.
Another object of the present invention is to provide a non-volatile semiconductor memory device having a structure suited for increasing an erasure speed of a MONOS or other memory transistor having a planarly dispersed charge storing means.
To achieve the first object, according to a first aspect of the present invention, there is provided a method of erasing a non-volatile semiconductor memory device having a memory transistor comprising a source region and a drain region formed on a surface portion of a semiconductor while sandwiching a channel-forming region there between, a gate insulating film provided on the channel-forming region and including dispersed charge storing means, and a gate electrode on the gate insulating film, the method comprising the steps of repeating a write-erase operation a plurality of times when erasing the memory transistor.
The method of erasing a non-volatile semiconductor memory device according to a second aspect of the present invention comprises, the steps of: performing an erase operation; and performing a write-erase operation at least once.
The method of erasing the non-volatile semiconductor memory device according to a third aspect of the present invention comprises, when erasing the memory transistor, the steps of: performing a write operation; and performing an erase operation.
The present invention is suitable for a separated source line NOR type and a NOR type non-volatile memory device with source lines and bit lines formed into hierarchies.
Further, concerning the memory transistor structure, the present invention is particularly suited to a MONOS type, a fine particle type having nanocrystals or other small size conductors, and other non-volatile memory transistors having the dispersed charge storing means formed to be dispersed at least in a surface direction facing the channel-forming region. These non-volatile memory transistors having planarly dispersed charge storing means are excellent in scaling of the tunnel insulating film in comparison with the FG type.
This memory device comprises the dispersed charge storing means does not have conductivity over an entire surface facing the channel-forming region at least when charges do not dissipate outside.
In the method of erasing a non-volatile semiconductor memory device according to the first and second aspects of the present invention, attention was paid to the fact that the convergence of the threshold voltage becomes higher in the case where one erasure time is shortened and the erase operation is repeated a plurality of times in the MONOS or other memory transistor.
For example, when erasing twice with a write operation in between, the threshold voltage converges considerably. Further, if a write-erase cycle is repeated at least twice, the convergence of the threshold voltage becomes even better. Accordingly, by applying this method of including a plurality of erase steps in one erasure operation, the total erasure time required for satisfying a predetermined convergence of the threshold voltage becomes shorter.
Note that the phenomenon of the convergence of the threshold voltage rising by a plurality of erasures is peculiar to the mechanism of operation of a MONOS type and does not exist in the FG type.
Accordingly, the method of erasing a non-volatile semiconductor memory device according to the third aspect of the present invention is fundamentally different in object from writing before erasure performed on the FG type for correcting the distribution of the threshold voltage in a wafer.
According to a fourth aspect of the present invention, there is provided a method of erasing a non-volatile semiconductor memory device having a memory transistor comprising a source region and a drain region formed on a surface portion of a semiconductor while sandwiching a channel-forming region there between, a gate insulating film provided on the channel-forming region and including dispersed charge storing means, and a gate electrode on the gate Insulating film, the method comprising the steps of: setting an erasure voltage and/or erasure time corresponding to the phenomenon of an absolute value of the voltage of an inflection point taking an extremum at the erasing side in a hysteresis curve of change shown the threshold voltage with respect to the applied voltage of the memory transistor becoming larger along with shortening of the voltage application time; and erasing the memory transistor by using that erasure voltage and/or erasure time.
Preferably, the erasure voltage is set within a range not exceeding the voltage of the inflection point in absolute value and the memory transistor is erased using the set erasure voltage and corresponding erasure time.
In this case, more preferably, the erasure voltage is set at the same value as the voltage of the Inflection point or between the voltage of the inflection point and the minimum voltage for generating an electric field required for causing the dispersed charge storing means to become saturated.
According to a fifth aspect of the present invention, there is provided a method of erasing a non-volatile semiconductor memory device having a memory transistor comprising a source region and a drain region formed on a surface portion of a semiconductor while sandwiching a channel-forming region there between, a gate insulating film provided on the channel-forming region and including dispersed charge storing means, and a gate electrode on the gate insulating film, the method comprising the steps of: setting the erasure voltage the same as the voltage of the inflection point taking an extremum at the erasing side in the hysteresis curve shown the change of threshold voltage with respect to the application voltage of the memory transistor or between the voltage of the inflection point and the minimum voltage for generating the electric field required for causing the dispersed charge storing means to become saturated; and erasing the memory transistor using the erasure voltage.
In the memory hysteresis characteristic, when the gate voltage of for example an nMOS transistor is made larger to a negative side, the amount of electrons injected from the gate electrode is increased relative to the amount of the holes injected from the substrate side into the charge storing means and the recombination region of the two changes in the thickness direction of the gate insulating film, so there is an inflection point at which the threshold voltage inverts from a reduction to increase.
The methods of erasing non-volatile semiconductor memory devices according to the fourth and fifth aspects utilize this phenomenon of the absolute value of the inflection point voltage becoming larger along with the shortening of the erasure time. That is, the shorter the erasure time, the greater the leeway for making the erasure voltage larger in absolute value and, as a result, the greater the erasure electric field and the higher the erasure efficiency.
The method of erasing a non-volatile semiconductor memory device according to a sixth aspect of the present invention comprises, in a single erasure operation of the memory transistor, the steps of: performing a plurality of erase operations including an erase operations using an erasure voltage the same as or smaller than, in absolute value, the voltage of the inflection point taking an extremum at the erasing side in a hysteresis curve shown the change of threshold voltage with respect to the applied voltage of the memory transistor while changing the erasure voltage and the erasure time.
This method of erasure is a combination of an increase of the erasure voltage based on the voltage of the inflection point and a plurality of erasures. By this, the total erasure time becomes further shorter.
In this case, for example, if the erasure time is short, erasure can be performed further faster using an erasure voltage exceeding the inflection point voltage. In general, if an erasure voltage exceeding the inflection point voltage is used, the threshold voltage after the erasure rises, but if the erasure time is short, this has almost no effect in reducing the difference in the threshold voltage between the erase state and the write state (threshold value window). Conversely, there is the large advantage of increasing the erasure voltage in absolute value and shortening the total erasure time.
To achieve the second object, according to a seventh aspect of the present invention, there is provided a non-volatile semiconductor memory device having a memory transistor comprising a source region and a drain region formed on a surface portion of a semiconductor while sandwiching a channel-forming region there between, a gate insulating film comprised of a tunnel insulating film, a nitride film, and a top insulating film sequentially stacked on the channel-forming region and including dispersed charge storing means in the stacked films, and a gate electrode on the gate insulating film, wherein thicknesses of the tunnel insulating film and the top insulating film are set so that the thickness of the gate insulating film converted to an oxide film becomes 10 nm or less and the change of the threshold voltage at the time of erasing the memory transistor is regulated by a recombination process of a hole current injected from the channel-forming region side and an electron current injected from the gate electrode side.
Preferably, the thickness of the tunnel insulating film is 2.5 nm or more, and a ratio of thickness of the top insulating film to the tunnel insulating film is 1.4 or more.
The voltage at which the inflection point appears is physically defined by a relative magnitude between the hole current injected from the channel-forming region side and the electron current injected from the gate electrode side, a recombination efficiency of electrons and holes, and a probability of catch and escape of the traps. This hole current and the electron current depend upon the specifications such as the thickness of the film constituting the gate insulating film (for example ONO film) in addition to the erasure conditions, that is, the erasure voltage and the erasure time.
In the non-volatile semiconductor memory device according to the present invention, the thickness conditions of the tunnel insulating film and the top insulating film among the films constituting this gate insulating film (for example ONO film) are defined so that the absolute value of the inflection point voltage easily becomes large. Accordingly, the erasure time for acquiring the threshold voltage of the predetermined erase state can be easily shortened in the structure.